In a non-source-synchronous system in which a first device and a second device communicate data and commands to each other on a communications bus, the first device may send a clock signal to the second device, but the second device may not send a clock signal to the first device. In these systems, when the first device receives a data signal from the second device, the first device may use its own clock signal to determine when to sample the data signal in order to identify the logic levels or bit values of the data signal.
The second device may generate and send the data signal based on the clock signal it receives from the first device. In that regard, each cycle of the data signal may correspond to a particular clock cycle of the clock signal sent by the first device. Accordingly, if the first device is to receive a data signal from the second device, the first device may expect to receive a given cycle of the data signal within a certain time period from the time the first device sent the corresponding clock cycle used to generate the given data signal cycle. That certain time period may be referred to as clock-to-data loop delay (or simply loop delay).
The amount of the loop delay may depend on trace length of the communications bus connecting the first device and the second device and the delay provided by the internal circuitry of the second device to receive the clock signal and generate the data signal. The amount of the loop delay may vary for different non-source synchronous systems. For example, internal circuitries of two second devices made by two different manufacturers or even two devices made by the same manufacturer may provide different amounts of delay. Additionally, loop delay may change at different points in time for a given system or a given second device due to changes in temperature or other environmental conditions.
When a second device connects to a first device for communication, it is critical that the first device identify the amount of loop delay so that it knows when to sample the received data signal. Absent such an identification may cause the first device to sample the data signal at improper times, which in turn may cause the first device to identify the wrong logic levels and associated bit sequence of the data signal.
To identify the amount of loop delay, and in turn optimal sample points at which to sample the data signal, the first and second devices may perform a tuning operation. In one example tuning scheme, the second device sends the first device data signal having a predetermined data pattern, and the first device identifies the sampling points upon recognition of the data pattern. The data pattern may be set according to a protocol, such as a secure digital (SD) protocol. In addition, the first device may utilize a timing window for recognizing the data pattern. In some configurations, the timing window may be measured in terms of unit intervals (UI), with one unit interval (1 UI) and two unit intervals (2 UI) being common timing windows, and where one unit interval may be equal to one clock period. Data signals used for tuning that arrive outside of the timing window may not be recognized by the first device. As such, one downside of performing tuning using a timing window is the occurrence of tuning errors for second devices that provide too large of a loop delay.
Current non-source-synchronous systems, such as SD systems where a host device communicates with a SD device, may communicate according to a single data rate (SDR) data transfer mode, where data is transferred on only one clock transition—either the rising edge or the falling edge. As media resolutions increase, it may be desirable for non-source synchronous systems to switch to a double data rate (DDR) data transfer mode—where data is transferred on both the rising edge and the falling edge of the clock signal—in order to increase the data rate at which data is communicated on the communications bus.
Systems other than non-source-synchronous systems that communicate using DDR may utilize a synchronous line (e.g., a strobe line) to communicate a synchronization signal from the second device to the first device along with the data signal on the data line. Common names for the synchronization signal may include Data Strobe, Enhanced Strobe and Returned Clock (RCLK). The first device may use the synchronization signal to determine when to sample the incoming data signal. However, non-source-synchronous systems, such as SD systems, do not use a synchronization signal, the communications bus connecting the first device and the second device does not include a synchronous line, and adding such a synchronous line may undesirably increase the cost for such systems.
As such, a new tuning scheme for non-source-synchronous systems that can be used for DDR data transfer and that do not depend on a timing window and/or a synchronous signal communicated on a synchronous line may be desirable.